a) Field of the Invention
The invention relates to a thin film transistor (TFT) array substrate in a flat-panel display device, such as a liquid crystal display device, and a method for manufacturing the TFT array substrate.
b) Description of the Related Art
In recent years, it has been prevailing over development of substitute products for cathode ray tube (CRT) flat-panel display devices. Up until now, among other things, liquid crystal display (LCD) devices, which have been developed from the purpose of small-size mobile displays to the purpose of large-size television displays, are the most popular and widespread.
The LCD device is an electro-optical device with liquid crystals sandwiched between two pieces of substrates. An active LCD device with excellent image quality mostly uses the array substrate, in which a plurality of data lines and scan lines are formed in grids on one surface of a transparent insulation substrate such as a glass substrate, and a thin film transistor (TFT) formed with semiconductor film like amorphous silicon as a switching element is provided at each intersect of the signal line and scan line. In order to manufacture the TFT array substrate, a plurality of photolithography processes that use photomasks are necessary, just as in manufacturing semiconductor integrated circuits. It is apparent that decreasing the number of the processes which include lithography processes benefits enhancement of the LCD production and reduction of cost.
Currently, active matrix amorphous silicon TFT array substrate is generally manufactured by a process including five or four lithography processes. One conventional technology, the half-tone photoprocess technology using four photomasks disclosed in Japanese Laid-Open Patent Publication JP2000-206571 (reference 1) and “A NOVEL FOUR MASK COUNTPROCESS ARCHITECTURE FOR TFT-LCDS” SID 2000, Digest of Technical Papers, Page 1006-1009, will be described below. It is a rationalized technology where the island-like process of a semiconductor layer including channels and the process of the source-drain wiring are performed through the half-tone exposure technology with one photomask.
FIGS. 1A to 5O are referenced to for the description of reference 1 in correspondence with the progress of the process; FIGS. 1 to 5 illustrate sectional portions of a scan line—data line intersection at which the data lines and the scan lines are arranged to intersect, a TFT section as a switching element, a pixel section, and an electrode terminal section arranged in circuits surrounding the scan lines.
First, as shown in FIG. 1A, chromium, molybdenum, tantalum, aluminum, copper, alloy thereof, or stacked layer is covered on one surface of a glass substrate 1 as a first metal film 2 by using a film preparation device such as a sputtering device. Second, photoresist is coated on a surface of the first metal film 2 and a photoresist pattern 3 as shown in FIG. 1B is selectively formed by using a first photomask. Third, the first metal film 2 is etched to remove the photoresist with the photoresist pattern 3 as a mask, and thus a gate film 2A functioning concurrently as a scan line as shown in FIG. 1C is formed. The thickness of the gate film 2A is generally set in a range of 0.1 to 0.3 μm.
Next, three films including a first silicon nitride film 4 as a gate insulation layer, an almost impurity-free first amorphous silicon (a-Si) film 5 as channels of transistor, and a second amorphous silicon film (N+a-Si) 6 doped with N-type impurities as the source-drain of transistor are covered with respective thickness of 0.3-0.2-0.05 μm by using a film preparation device such as the plasma chemical vapor deposition (CVD) device or sputtering device. Further, chromium, molybdenum, tantalum, aluminum, copper, alloy thereof, or stacked layer is covered as a second metal film 7 by the sputtering device; the thickness of the second metal film 7 is generally around 0.3 μm. After that, a second photomask that adjusts the transmittable exposure energy with slit pattern and dot pattern, or with semi-transmitting film, is used to form an unexposed portion, a fully exposed portion, and a half-tone exposed portion, so as to prepare a photoresist pattern 8 with a thickness varied according to the region, as shown in FIG. 2E. In FIG. 2E, the part denoted as 8A indicates the channel section patterned by half-tone exposure method, which is characterized by the smaller thickness of the channel section 8A than other regions corresponding to the source-drain wiring. Then, as shown in FIG. 2F, the second metal film 7, the second silicon film 6 and the first silicon film 5 are etched by using the photoresist pattern 8 as a mask to form the source-drain wiring and expose the gate insulation layer 4A. Next, by using the oxygen plasma ashing method, the photoresist in the channel section 8A is removed and the data line layer 7 is exposed, as shown in FIG. 3G The photoresist pattern 8B with reduced thickness is then used as a mask to again etch the data line layer 7, the second silicon film 6, and the first silicon film 5, then the second silicon film 6 between the source-drain wiring is removed so that the thickness of the first silicon film 5 remains around 0.05-0.1 μm, as shown in FIG. 3H. In other words, the almost impurity-free first silicon film is selectively formed to be the channels of TFT, and concurrently the source-drain wiring (SD wiring) 7A, 7B are separated. Thereafter, the photoresist pattern 8B is removed as shown in FIG. 31.
Then, as shown in FIG. 4J, a protection film or a passivation layer 9 like a second silicon nitride film with a thickness of 0.3 μm, is covered by sputtering or CVD, and a photosensitive acrylic resin film 10 is further coated as a planarization film for flattening the surface of the array substrate 1. In general, the planarization film is coated to have a thickness of more than 3 μm. After that, as shown in FIG. 4K, through holes 10A, 10B for reaching the first metal film 2A and the second metal film 7B are formed with a fourth photomask. Subsequently, as shown in FIG. 4L, the insulation films in the through holes 10A, 10B, which are the second silicon nitride film 9 and the first silicon nitride film 4, are etched so that the first metal film 2A and the second metal film 7B are partially exposed.
Next, as shown in FIG. 5M, a transparent conductive film 11 is covered to be formed on the whole surface of the glass substrate 1 by such as sputtering or coating method. The transparent conductive film 11 is generally a metal oxide film like indium tin oxide (ITO), indium zinc oxide (IZO) or mixture thereof. Then, a pixel electrode 11A is patterned via selectively etching the transparent conductive film 11 by using a fifth photomask with a photoresist pattern 12 shown in FIG. 5N as a mask. Afterward, the unwanted photoresist pattern 12 is removed and the glass substrate 1 becomes an array substrate for an active matrix a-Si TFT, as shown in FIG. 5O.
The TFT array substrate thus obtained is bonded with a color filter to form a liquid crystal panel, and then backlight and driving circuit board are assembled as a liquid crystal module, so as to construct various liquid crystal display devices. The aforementioned method for manufacturing an array substrate of the active matrix a-Si TFT requires four photomasks. However, a process reduction technology disclosed in Japanese Laid-Open Patent Publication JP2002-250935 (reference 2) creates the contact formation process as shown in FIG. 4 and the pixel electrode formation process as shown in FIG. 5 by water-repellent treatment technology with one photomask, wherein three photomasks are employed in total to form a TFT array substrate. In addition, similarly, another process reduction technology disclosed in Japanese Laid-Open Patent Publication JP2002-98996 (reference 3) also creates two aforementioned patterning processes by chemical mechanical polishing treatment with one photomask, wherein three photomasks are employed in total to form a TFT array substrate.